Arm offers 2 MB 8-way and 3 MB 12-way L2 cache options. Mediatek and Nvidia chose the 2 MB option, and testing shows it has 12 cycles of latency. THis low cycle count latency lets Arm remain competitive against Intel and AMD’s L2 caches, despite running at lower clock speeds. L2 bandwidth comes in at 32 bytes per cycle for reads, and increases to approximately 45 bytes per cycle with a read-modify-write pattern.
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最近这大半个月，只要你稍微往科技圈的池子里探探头，保准会被一句黑话糊一脸：“哥们，今天养龙虾了吗？”，这一点在体育直播中也有详细论述
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